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Replacement Ratios Preretirement Income ($000) $20 30 40 50 60 70 80 90 Social Security (%) 65 56 51 48 43 39 35 33 Private and Employer Sources (%) 24 28 29 29 32 37 42 45

x'(7..0) 0

It should be noted that to represent the fractional number properly, some other device such as an external microprocessor will need to provide an initial

Total (%) 89 84 80 77 75 76 77 78

9-bit adder x''(8..0) 239(273)

inversion. If an external device is de ning the divisor, this method can work well. If the divisor is determined by some other logic and the design does not have the luxury of this representation, then other methods will be required as described in the following sections.

Source: Aon Consulting, Inc. and Georgia State University, Replacement Ratio Study: A Measurement Tool for Retirement Planning (Illinois: Aon Consulting, Inc, 2004), 3.

x(15..12)&0&x(15..12) 0 0 x''(7..0)

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The division algorithm discussed in this section is an example of an algorithm that falls into a class of digit recurrence methods. Iterative methods typically refer to successive approximation methods (discussed in the next section), but for consistency with other chapters, we will refer to this as an iterative method as it maps to similar iterative methods used for compact implementations of other functions. Iterative division works much like long division with decimal numbers did in elementary school. One of the advantages in using binary numbers, however, comes from the fact that certain optimizations can be made in the division process. Take the following long division example with the binary representations of 2 divided by 3 as shown in Figure 8.3. The divider for a xed-point number can be architected as shown in Figure 8.4 with a comparator and a subtraction unit. With this architecture, the dividend is normalized to a xed-point value that is necessarily smaller than twice the divisor. By doing this, every subsequent shift operation will produce a new partial quotient that must be less than twice the divisor. This means that the divisor will go into the partial quotient 1 or 0 times. If the divisor is less than or equal to the partial dividend for the current iteration, a logic-1 is shifted into the quotient register, otherwise, a logic-0 is shifted in and the partial dividend is shifted left by 1. After the necessary number of iterations to achieve the desired precision, the output is postnormalized to shift the data to the proper xed-point location (undo the prenormalization).

Table 6.2 illustrates three significant points about the replacement ratio calculations: 1. Social Security replaces a larger portion of preretirement income at lower wage levels. This is by design and has the effect of redistributing income from higher-paid employees to lower-paid ones. 2. Total replacement ratios are highest for the very lowest-paid employees. This is because these employees save the least and pay the least in taxes (as a percentage of income) before retirement. Thus, they spend a higher percentage of their income and need higher replacement ratios to maintain that level of expenditures. 3. After reaching an income level of $60,000, total replacement ratios begin to increase slowly. This is primarily because postretirement taxes increase as income levels increase. Postretirement taxes increase from 0.7 percent of postretirement income for a person earning $60,000 to 9.3 percent for a person earning $90,000. To pay the additional taxes, higher-paid employees need more retirement income.*

The most effective and widely used technique for lowering the dynamic power dissipation in synchronous digital circuits is to dynamically disable the clock in speci c regions that do not need to be active at particular stages in the data ow. Since most of the dynamic power consumption in an FPGA is directly related to the toggling of the system clock, temporarily stopping the clock in inactive regions of the design is the most straightforward method of minimizing this type of power consumption. The recommended way to accomplish this is to use either the clock enable pin on the ip- op or to use a global clock mux (in Xilinx devices this is the BUFGMUX element). If these clock control elements are not available in a particular technology, designers will sometimes resort to direct gating of the system clock. Note that this is not recommended for FPGA designs, and this section describes the issues involved with direct gating of the system clock.

Observe that if x x(15) x(14) . . . x(0) and x0 x0 (9) x0 (8) . . . x0 (0), then x2 x(15)x(14)x(13)x(12), x1 x(11)x(10)x(9)x(8), x0 x(7)x(6) x(0),

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